The Complete Cadence Design Flow Cheatsheet: IC Design from Concept to Tape-out

Introduction: Understanding Cadence and Integrated Circuit Design Flow

Cadence Design Systems provides a comprehensive suite of Electronic Design Automation (EDA) tools that enable the design, verification, and implementation of integrated circuits (ICs), System-on-Chips (SoCs), and printed circuit boards (PCBs). The Cadence workflow encompasses the entire semiconductor design process from concept to manufacturing.

This cheatsheet provides a comprehensive guide to the Cadence IC design flow, covering:

• The complete design cycle from specification to tape-out
• Key tools in the Cadence ecosystem and their roles
• Essential commands, shortcuts, and methodologies
• Best practices for efficient IC design
• Common challenges and their solutions

Core Cadence Tools and Their Functions

Comprehensive Cadence IC Design Flow

1. Specification and Planning

• Requirements Analysis

  • Define functional specifications
  • Determine performance targets (speed, power, area)
  • Identify target technology node
  • Establish design constraints

• Architecture Planning

  • Block-level partitioning
  • Memory architecture
  • Interface definition
  • Clock domain planning
  • Power domain strategy

• Design Planning Checklist

  • [ ] Technology node selected
  • [ ] IP blocks identified
  • [ ] Design hierarchy established
  • [ ] Floorplan strategy outlined
  • [ ] Power/ground distribution planned
  • [ ] Clock distribution strategy defined

2. RTL Design and Functional Verification

RTL Development with Genus™

# Basic Genus flow commands
read_hdl -sv {top.sv module1.sv module2.sv}
elaborate
set_top_module top_module
set_dont_use [get_lib_cells */COMPLEX_CELLS/*]
set_clock_gating_style -sequential_cell latch
syn_generic
syn_map
syn_opt
write_hdl > top_netlist.v

Functional Verification with Xcelium™

# Basic Xcelium simulation commands
xrun -compile -sv top_tb.sv
xrun -elaborate -sv top_tb.sv
xrun -sv top_tb.sv -access +rwc -gui

• Verification Strategies

  • Directed testing
  • Constrained-random verification
  • Coverage-driven verification
  • Assertion-based verification

• Formal Verification with JasperGold®

  • Equivalence checking
  • Property checking
  • Protocol compliance

3. Logic Synthesis

Synthesis Flow (Genus™)

1. Pre-Synthesis Steps

   • Read and analyze HDL files
   • Elaborate design
   • Set design constraints
   • Apply clock definitions

2. Optimization Steps

   • Technology mapping
   • Area optimization
   • Timing optimization
   • Power optimization

3. Post-Synthesis Steps

   • Generate netlist
   • Create timing reports
   • Perform quality checks
   • Export for implementation

# Setting timing constraints in Genus
create_clock -name clk -period 10 [get_ports clk]
set_input_delay 2 -clock clk [all_inputs -filter {name != clk}]
set_output_delay 3 -clock clk [all_outputs]
set_max_transition 1 [current_design]

4. Floorplanning and Power Planning

Innovus™ Implementation System

# Basic floorplanning commands
init_design
floorPlan -site core -r 0.8 0.7 20 20 20 20
add_rings -type core_rings -nets {VDD VSS} -width 2 -spacing 1
add_stripes -direction vertical -nets {VDD VSS} -width 1 -spacing 2
editPin -pin [all_inputs] -layer M1 -side left -spacing 2
editPin -pin [all_outputs] -layer M1 -side right -spacing 2

• Key Floorplanning Considerations

  • Die size and aspect ratio
  • Core utilization target
  • Macro placement
  • I/O planning
  • Power grid planning
  • Clock distribution network

• Power Planning Strategy

  • Power ring definition
  • Power stripe creation
  • Power domain separation
  • Low-power design techniques

5. Placement and Optimization

# Placement commands
place_design
optDesign -preCTS
saveDesign pre_cts.enc

• Placement Methods

  • Global placement
  • Detailed placement
  • Macro placement
  • Congestion-driven placement
  • Timing-driven placement

• Optimization Techniques

  • Buffer insertion
  • Gate sizing
  • Cell swapping
  • Fanout optimization
  • High-fanout net synthesis

6. Clock Tree Synthesis (CTS)

# Clock tree synthesis commands
ccopt_design
optDesign -postCTS
report_clock_tree
verify_clock_tree

• CTS Objectives

  • Minimize clock skew
  • Reduce insertion delay
  • Control clock transition
  • Manage power consumption
  • Handle multiple clock domains

• Clock Tree Structures

  • H-tree
  • Balanced tree
  • Clock mesh
  • Hybrid approaches

7. Routing and Optimization

# Routing commands
routeDesign
optDesign -postRoute
addFiller
verify_drc
extractRC
timeDesign -postRoute

• Routing Stages

  • Global routing
  • Track assignment
  • Detailed routing
  • Special net routing
  • ECO routing

• Post-Route Optimization

  • Timing closure
  • Signal integrity fixes
  • DRC violation fixes
  • Crosstalk mitigation
  • IR drop optimization

8. Custom/Analog Design with Virtuoso®

Schematic Design

• Key Commands

  • Create new cell: File > New > Cell View
  • Edit properties: q key
  • Wire components: w key
  • Add instance: i key
  • Add pin: p key

• Design Hierarchy Management

  • Create symbols for subcircuits
  • Build hierarchical designs
  • Use parameterized cells

Layout Design

• Basic Layout Commands

  • Create rectangle: r key
  • Create path: p key
  • Create polygon: Shift+p
  • Move objects: m key
  • Copy objects: c key
  • Stretch objects: s key

• Advanced Layout Techniques

  • Guard rings
  • Common centroid layouts
  • Interdigitation
  • Dummy structures
  • Shielding techniques

9. Physical Verification

Design Rule Checking (DRC)

# Run DRC in Virtuoso with Pegasus
drcCheck(
    viewName = "layout"
    rulesFile = "rules.drc"
    switches = ""
)

Layout vs. Schematic (LVS)

# Run LVS in Virtuoso
lvs(
    sourceViewName = "schematic"
    targetViewName = "layout"
    sourceNetlist = "source.net"
    targetNetlist = "target.net"
    rulesFile = "rules.lvs"
    switches = ""
)

Parasitic Extraction

# Run extraction with Quantus
extractRCmode(
    viewName = "layout"
    rulesFile = "rcx.rules"
)

10. Static Timing Analysis with Tempus™

# Basic Tempus STA commands
read_lib tech.lib
read_verilog netlist.v
read_sdc constraints.sdc
update_timing
report_timing -max_paths 10

• Key Timing Checks

  • Setup time
  • Hold time
  • Recovery/removal time
  • Pulse width
  • Clock-to-q delay

• Advanced Timing Analysis

  • On-chip variation (OCV)
  • Multi-corner multi-mode (MCMM) analysis
  • Statistical static timing analysis (SSTA)
  • Common path pessimism removal (CPPR)

11. Power Analysis with Voltus™

# Basic Voltus commands
read_power_intent power_intent.upf
analyze_power -dynamic -static
report_power

• Power Analysis Types

  • Static power analysis
  • Dynamic power analysis
  • IR drop analysis
  • EM/reliability analysis

• Power Optimization Techniques

  • Clock gating
  • Power gating
  • Multi-voltage design
  • Dynamic voltage scaling

12. Sign-off and Tape-out

• Final Verification Steps

  • Multi-corner timing closure
  • Final DRC/LVS clean
  • EM/IR verification
  • Antenna checks
  • Design for manufacturing (DFM) checks

• Tape-out Package Generation

  • GDSII stream-out
  • LEF/DEF generation
  • Final documentation
  • Signoff database archiving

Common Challenges and Solutions

Best Practices for Cadence Design Flow

Design Setup Best Practices

• Use consistent directory structure across projects
• Implement proper version control for all design files
• Create and maintain technology setup files
• Document design constraints and assumptions
• Establish clear naming conventions

RTL Design Best Practices

• Follow synchronous design principles
• Implement proper clock domain crossing
• Use consistent coding style
• Create modular, reusable blocks
• Document interfaces thoroughly

Verification Best Practices

• Create comprehensive test plans
• Implement systematic coverage metrics
• Use assertions for critical properties
• Employ both directed and random testing
• Verify corner cases explicitly

Physical Design Best Practices

• Build realistic timing constraints
• Plan for multiple implementation iterations
• Create margin for late-stage ECOs
• Implement progressive refinement methodology
• Account for manufacturing variability

Analog Design Best Practices

• Use parameterized cells
• Implement design reuse
• Create robust designs with margin
• Verify across all process corners
• Document design assumptions

Recommended Cadence Shortcuts and Aliases

Virtuoso Shortcuts

Useful Tcl Aliases for Innovus™

# Add these to your .cdsinit or project startup files
alias save "saveDesign"
alias opt "optDesign -preCTS"
alias optcts "optDesign -postCTS"
alias optroute "optDesign -postRoute"
alias report_worst "report_timing -max_paths 10"
alias check_design "checkDesign -all"

Resources for Further Learning

Official Cadence Resources

• Cadence Support Portal (https://support.cadence.com)
• Cadence Online Training
• Cadence User Conferences (CDNLive)
• Cadence Application Notes and White Papers

Community Resources

• Cadence Community Forums
• EDA Playground (for Verilog/VHDL)
• Reddit r/FPGA and r/ECE
• Twitter #CadenceEDA

Books and Publications

• “Digital Integrated Circuit Design Using Verilog and Systemverilog” by Ronald W. Mehler
• “CMOS Digital Integrated Circuits” by Sung-Mo Kang and Yusuf Leblebici
• “Static Timing Analysis for Nanometer Designs” by Jayaram Bhasker and Rakesh Chadha
• “Low Power Methodology Manual” by Keating, et al.

Additional Learning Materials

• IEEE Papers on IC Design Methodologies
• ISSCC Conference Proceedings
• DAC Conference Papers
• VLSI Journals and Transactions

This cheatsheet provides a comprehensive overview of the Cadence IC design flow, from specification to tape-out. While it covers the essential aspects of the design process, IC design is a complex field that requires continuous learning and adaptation to new technologies and methodologies. Regular updates to tools and design techniques are essential to stay current with the evolving semiconductor industry.